1. Field of Invention
The present invention relates to a method for manufacturing dynamic random access memory (DRAM). More particularly, the present invention relates to a method for manufacturing DRAM capacitor.
2. Description of Related Art
As semiconductor manufacturing passes into the deep submicron scale, dimensions of each device shrink. Hence, a higher operating speed for each integrated circuit results. For an integrated circuit with the same device layout, operating speed is closely related to density of the devices. In a high-density integrated circuit such as DRAM, distance of separation between a node contact of the capacitor and its neighboring bit lines is correspondingly reduced. Therefore, how to maintain good isolation between the node contact and bit lines despite their increasing closeness is a major problem waiting to be resolved.
To maintain good isolation between a node contact and a bit line, DRAM capacitors are conventionally formed by a polysilicon-spacer reduced contact method or a self-aligned contact (SAC) method is used. What the polysilicon-spacer reduced contact method aims for is a reduction of the dimensions of a node contact so that thickness of an insulation layer between the node contact and the neighboring bit lines is increased. The method involves forming a polysilicon layer over an insulation layer and forming an opening of designated dimensions in the polysilicon layer. This is followed by forming polysilicon spacers on the sidewalls of the opening, thereby reducing size of the opening. Using the polysilicon layer and the polysilicon spacers as a mask, the insulation layer is etched to form a smaller node contact opening. Through the reduction of node dimensions, subsequently formed node contact is further apart from adjacent bit lines by a thicker intervening insulation layer. Hence, a better insulation between the node contact and the bit line is achieved.
In the self-aligned contact method, silicon nitride cap layer and silicon nitride spacers are formed on respective top surface and sidewalls of a bit line so that the bit line is entirely enclosed. An insulation layer is formed over the bit lines and underlying substrate layer. The insulation layer is patterned so that a node contact opening is formed between two neighboring bit lines. Due to the presence of the silicon nitride layer around the bit lines, good insulation between the bit line and the node contact is ensured.
However, the two aforementioned methods manage to form node contact openings only. A photomask is still needed to pattern out a lower electrode with the desired shape at designated locations above the insulation layer. Since some more processing steps are required to complete the fabrication of the capacitor, more time is consumed and additional costs are incurred.